UTILIZING BUILT-IN SELF-TEST ARCHITECTURE FOR WEIGHTED PSEUDO RANDOM TEST PATTERN GENERATOR IMPLEMENTATION

Abstract

Expanded chip capabilities is a notable need as submicron technology develops. Due to the current generation's mass production of ICs, thorough testing is necessary to separate the good chips from the poor. Verification Engineers must comprehend the operation of the chip in order to perform a comprehensive verification and find any flaws in the product. Because they demand a significant time investment and circuit complexity, conventional testing methods are not adequate for the current generation. As a result, it becomes necessary to automatically create test patterns with a high level of variability in between them. The randomness that is employed to generate the test pattern is provided by Galois fields. A weighted test pattern generator has also been used.