Approximate computing is a new paradigm for nanoscale technologies that overcomes the problem of mistake tolerance in computation, allowing for greater performance with less power. The 3-input MV is an important building component of majority logic (ML) in digital circuit design and is expected to play a significant role in numerous emerging nanotechnologies. In order to do this, the suggested multipliers and adders employ approximation compressors and a reduction circuitry that makes use of so-called complement bits. An approach is provided for selecting appropriate complement bits, and a size-dependent multiplier-dependent effect factor is developed and studied. The proposed designs are evaluated based on their feasibility using hardware metrics (such delay and gate complexity) and error metrics. The proposed designs are proved to be superior than existing ML-based systems in the literature. Case studies of bug-free programs are offered to show that the suggested architectures work as advertised