Low power has arisen as a chief subject in this day and age of hardware ventures. Power dispersal has turned into a significant thought as execution and region for VLSI Chip plan. With contracting innovation lessening power utilization and over all power the board on chip are the vital moves underneath 100nm because of expanded intricacy. For some plans, streamlining of force is significant as timing because of the need to lessen bundle cost and expanded battery duration. For power the board spillage current additionally assumes a significant part in low power VLSI plans. Spillage current is turning into an undeniably significant part of the all out power dispersal of incorporated circuits. This paper portrays about the different procedures, strategies and power the executive’s methods for low power circuits and frameworks. Future difficulties that should be met to plans low power superior execution circuits are additionally talked about.