Versatile Video Coding is a new international image compression standard developed to provide high compression factor compared to previous standards like H.E.V.C,H,264 . VVC uses various DCT algorithms for image compression & IDCT algorithms for reconstruction, VVC provides better compression factor at expense of high computational complexity. This paper presents an approach for hardware implementation of 8X8 DCT,IDCT modules in Design 1, in which a 512x512 pixel image is fed as input to the DCT module and it is retrieved at IDCT.As VVC implementation utilizes hardware resources at higher expense this paper mainly focuses on reconstruction off image, reduction of resources especially multipliers .In order to reduce multipliers count a methodology has been implemented in Design 2[1].To eliminate multipliers completely a methodology has been implemented in Design 3 through adding and shifting operations. In order to reduce adders and shifters count a methodology has been proposed and implemented in Design 4. The proposed methodology reduces 4 stages of shifting and adding operations to 2 stages with complete elimination of multipliers. All the Designs implemented in this paper can generate 64 Transformed coefficient per Cycle [2]. The design implemented in proposed methodology can be utilized in high performance area efficient low power VVC modules. All the four Designs are simulated and synthesized in Xilinx Vivado 2019.2 shows that the simulation results are same for all the implemented Designs[3]. However Synthesis reports shows that the Proposed methodology is ideal as the hardware utilization is low which has been implemented on FPGA (Zed Board).