Application-specific integrated circuits and commercial CPUs need less power when the size of technological nodes lowers. Implementing power-saving measures is universally acknowledged as the most successful way for VLSI systems, both now and in the future. These devices have large on-chip SRAM memories. In current systems, it is critical to reduce power consumption due by memory leakage while maintaining data integrity. Unfortunately, advanced approaches such as power-gating are limited to logic applications due to their ability to wipe the data stored in an SRAM device. Previous research has found significant time and space concentrations of data patterns in commercial processors and application-specific integrated circuits (ICs) that process audio, video, and image data. This work describes a new columnar Energy Compression technique for deactivating cells depending on a data pattern, hence preserving power in SRAM. This technique applies to commercial processors and is used to investigate energy conservation in application-specific integrated circuit SRAM memories. The study also assesses the impact of pre-storage photo processing and data cluster architectures on power reductions in order to optimise power consumption