Unexpected phase connections between clock pulses are possible. Under these situations, clock synchronization is critical for data transfer via modules. We create a novel mesochronous first input-first output (FIFO) dual buffer capable of managing both synchronized and interim storage solutions by autonomously synchronizing data and manually synchronizing only the flow-control signals. The proposed architecture could work. Fully synchronized clocking is being substituted with more adaptive clocking techniques, such as mesochronous clocking, to increase device composability and time elimination. Despite the fact that the transmitter and receiver are separated by a long cable with a delay that does not correspond to the specified operating frequency, the module gets an identical clock signal on both ends of a mesochronous connection and runs at the same clock rate in this configuration. In such cases, the suggested mesochronous FIFO can be built in modular fashion to account for multi-cycle connectivity latencies while retaining the basic principle. Adopting the new architecture is expected to be much less expensive than the current triple mesochronous FIFO systems used by the government. The study also demonstrated the power, latency, and storage efficiency of data widths of 32 and 64 bits.