Advanced Encryption Standard (AES) is a specification for electronic data encryption. This standard has become one of the most widely used encryption method and has been implemented in both software and hardware. Field-programmable gate array (FPGA) is growing as a new platform for accelerating heavy computational tasks such as machine learning and cryptography. AES has excellent resistance against linear and differential cryptanalysis. But it can be vulnerable to attackers through side channels. Masking methods are popularly used to defend against power side channel attack (PSCA). This paper presents Design and implementation of High Performance, Low Power Masked 128-AES using FPGA. This masked design is implemented in Xilinx ISE 14.1 Project Navigator for synthesis and simulation. The experimental results show that our proposed design takes up less hardware resources and has the ability to defend against power side channel attack.