The quantity of power squandered by VLSI circuits has been a serious issue in recent years. The Adiabatic logic approach is emerging as a solution to the power dissipation issue. The word 'Adiabatic' alludes to a condition change which happens without energy being lost or gained. This adiabatic switching approach significantly minimizes the amount of energy lost during switching occurrences. However, adiabatic circuits are very dependent on fluctuations in the power clock as well as parameter values. The low-power adiabatic logic based ECRL circuit works largely in the sub threshold domain and consumes less power than a CMOS version. The article explores and develops ECRL-based sub-threshold induced adiabatic circuitry on a 6:3 counter component. Tanner had been used to execute the suggested design, and the simulated results for the 45 nm cmos technology are shown.