With increasing logic density being encapsulated in modern-day processing electronic chips, verification has been an increasingly taxing endeavour with enormous engineering and human resources to validate the integrity of design Intellectual Property modules. The primary simulation-driven testbench environment is not supporting exhaustive assessment to the stringent adherence to specifications, and these missed bugs percolate to the silicon stage, making defective chips. This paper demonstrates the successful deployment of a robust novel Formal Verification based methodology for verifying of RTL Design Code of the RISC Processor. The proposed methodology is also complemented with visualization of relevant quantitative signoff metrics for capturing insights about quality of Hardware Description Language (HDL) Code aiding in reducing time for RTL Freeze.