The main problem with current generation VLSI testing is test power. It has grown to be the SoC's top worry today. The modular design strategy in SoC (i.e., utilisation of IP cores in SoC) has further exacerbated the test power issue while lowering design efforts. It is difficult to choose a successful low-power testing method from a wide range of various techniques that are readily available. In this study, the state of the art in low-power testing is described, starting from the vocabulary and models for power consumption during test, to determine the appropriate solutions for test power reduction approach for IP core-based SoC. The study provides a thorough analysis of the numerous power reduction approaches suggested for all testing aspects, including built-in self-testing procedures, external testing,