The three-stage comparator and its updated version, which is intended to increase speed and decrease kickback noise, are presented in this project proposal. The three-stage comparator used in this work contains an additional amplification stage, which boosts speed and voltage gain when compared to conventional two-stage comparators. The three-stage comparator further increases the speed by enabling the use of nMOS input pairs in both the regeneration and amplification stages, in contrast to the conventional two-stage structure that employs pMOS input pair in the regeneration stage. Additionally, the amplification stage of the suggested modified three-stage comparator adopts a CMOS input pair. By cancelling out the nMOS kickback through the pMOS kickback, this significantly lowers the kickback noise. In the regeneration stage, it also adds an additional signal path, which contributes to an even faster speed improvement