This research proposes new circuits for XOR/XNOR and simultaneous XOR–XNOR functionality. The recommended circuits can run with very little power consumption and delays because to reduced output capacitance and short-circuit power dissipation. In addition, we propose six novel hybrid 1-bit full-adder (FA) circuits based on the state-of-the-art full-swing XOR–XNOR or XOR/XNOR gates. Each of the proposed circuits has advantages of its own in terms of speed, power consumption, power delay product (PDP), driving capabilities, and other characteristics. Comprehensive HSPICE and Cadence Virtuoso simulations are performed to evaluate the performance of the proposed designs. The simulation findings demonstrate that the proposed designs outperform competing FA solutions in terms of speed and power, based on Tanner, a 16-nm CMOS process technology model. A new method of sizing transistors is presented to optimize the PDP of the circuits. The suggested method minimizes the number of iterations needed to obtain the goal value for the optimal PDP by using a particle swarm optimization technique for numerical calculation. Regarding the recommended circuits, variations in the supply and threshold voltages, output capacitance, input noise immunity, and transistor size are investigated.