NOISE-AWARE, LOW-POWER THREE-STAGE COMPARATOR WITH FULLY DYNAMIC ERC INTEGRATION (International Journal of Food and Nutritional Sciences, 2022)
A three-stage comparator and its updated version are shown in this suggested project in order to increase speed and decrease kickback noise. The three-stage comparator in this study features an additional amplification step, which boosts the voltage gain and speed in comparison to the conventional two-stage comparators. The three-stage comparator increases speed by enabling the use of nMOS input pairs in both the regeneration and amplification stages, in contrast to the conventional two-stage construction that employs pMOS input pairs in the regeneration stage. Additionally, a CMOS input pair is used at the amplification step of the suggested modified three-stage comparator. By cancelling out the nMOS kickback through the pMOS kickback, this significantly lowers the kickback noise. In the regeneration step, it also provides an additional signal line, which aids in speeding up even more. Both the suggested three-stage comparators and the traditional two-stage comparators are built in the same CMOS process for convenience. The redesigned three-stage comparator increases speed, according to measured data. In this article, a new energy-efficient revolutionary voltage comparator known as an edge-race comparator (ERC) is presented, further enhancing this idea. By creating two propagating edges in two inverter loops and measuring the separation between them, it compares the differential input voltage. The winner is ultimately decided when the two edges race against one another. The comparator doesn't need high-voltage headroom and has low power and noise. By automatically adjusting its delay, power consumption, and noise according on the input voltage, it can reduce noise in fine comparisons and save a substantial amount of time and energy in coarse comparisons.