Design and Implementation of High-Speed Vedic Multiplier Architectures Using Optimized Adder Topologies for Efficient VLSI Systems. International Journal of Food and Nutritional Sciences, [S. l.], v. 11, n. 11, p. 2413–2421, 2022. Disponível em: http://ijfans.org/index.php/Journal/article/view/12736. Acesso em: 24 aug. 2026.