DESIGN AND IMPLEMENTATION OF PARALLEL PREFIX ADDER FOR HIGH SPEED AND LOW POWER APPLICATIONS (International Journal of Food and Nutritional Sciences, 2022)
ABSTRACT: Adder in general is a digital block used to perform addition operation of given data and generates the results as sum and carry-out. Adders are most widely used in different types of processors and other digital circuits. In today’s digital world, adder plays an important role in most of the digital circuits because of their use as basic entity in other operations such as subtraction, multiplication and division. Now-a-days, where everybody is working in the direction of miniaturization, three important aspects of design i.e area, power and delay needs to be balanced optimally. Low power and area efficient high-speed circuits are most substantial area in the research of VLSI design. So, improving the performance of basic component (adder) would greatly advance the performance of the whole digital system, which is the ultimate goal of VLSI. Use of conventional adders like ripple carry adder, carry save adder and carry look ahead adder are not used/implemented for industry and research applications, on the other hand the parallel prefix adders became popular with their fast carry generation network. In this analysis, design and implementation of Parallel Prefix Adder for high speed and low power applications is presented. The area, delay and power consumption will be measured. The area of the adder design is given in terms of Look Up Tables (LUT’s).